An HVIC of an element separation type that utilizes high-voltage junction is used as means for driving a switching power device that configures an upper arm of a power reverse conversion (AC-DC conversion) bridge circuit of a PWM inverter or the like. The HVIC can accomplish high functionality by detecting an overcurrent when the switching power device malfunctions and having temperature detecting means, and can achieve reductions of the size of a power supply system and lowering the costs by not performing potential insulation using a transformer or a photo coupler.
FIG. 9 is an explanatory diagram illustrating an example of connection between a switching power device of a power conversion device such as an inverter and a conventional HVIC that drives the switching power device. FIG. 9 shows an example of a half bridge in which two switching power devices (IGBT 114, 115) are connected to each other in series. The power conversion device shown in FIG. 9 alternately outputs a high potential or a low potential from a Vs terminal, which is an output terminal, by alternately turning the upper arm IGBT 115 and the lower arm IGBT 114 on, to supply an AC power to an L load 118 (run an AC current).
In other words, when outputting a high potential, the IGBT 114 and the IGBT 115 are operated in a manner that the upper arm IGBT 115 is turned on and the lower arm IGBT 114 is turned off. When outputting a low potential, on the other hand, the IGBT 114 and the IGBT 115 are operated in a manner that the upper arm IGBT 115 is turned off and the lower arm IGBT 114 is turned on. Note that FWDs (Free Wheel Diodes) 116, 117 are connected in inverse-parallel to the IGBT 114, 115. Meanwhile, in an HVIC 111, which is a drive element, a gate signal is output to the lower arm IGBT 114 with reference to GND, and a gate signal is output to the upper arm IGBT 115 with reference to the Vs terminal. For this reason, the HVIC 111 needs to be provided with a level shift function.
It should be noted that referential mark Vss in FIG. 9 represents a high-potential side of a high-voltage power supply, which is a main circuit power supply. Referential mark GND represents a ground (earth ground). Referential mark Vs represents an intermediate potential that fluctuates between the Vss potential and a GND potential. Referential mark H-VDD represents a high-potential side of a Vs-based second low-voltage power supply. Referential mark L-VDD represents a high-potential side of a GND-based first low-voltage power supply. In a bootstrap diode (a diode 75 shown in FIG. 2) circuit, the second low-voltage power supply is created from the first low-voltage power supply (L-VDD). Reference numeral 113 represents a high-side power supply and 112 a low-side power supply.
Furthermore, referential mark H-IN represents an input signal/input terminal that is input to a gate of a low-side C-MOS circuit, which is connected to a level-up circuit. Referential mark L-IN represents an input signal/input terminal that is input to a gate of the low-side C-MOS circuit, which is connected to a gate of the lower arm IGBT 114. Referential mark H-OUT represents an output signal/output terminal of a high-side C-MOS circuit, the output signal/output terminal being output to a gate of the upper arm IGBT 115. Referential mark L-OUT is an output signal/output terminal that is output to the gate of the lower arm IGBT 114. Referential mark ALM-IN represents an input signal/input terminal of a detection signal 119 that is obtained when the temperature of the upper arm IGBT 115 or an overcurrent is detected. Referential mark ALM-OUT represents an output signal/output terminal of a level-downed detection signal.
FIGS. 10 and 11 are each a circuit diagram showing a level shift circuit inside the HVIC 111 shown in FIG. 9, and a peripheral circuit of this level shift circuit. FIG. 10 is a circuit diagram that includes a level-up circuit. FIG. 11 is a circuit diagram that includes a level-down circuit. In FIGS. 10 and 11, reference numeral 120 represents a terminal on the high-potential side of the Vs-based second low-voltage power supply.
In the following description, “p” means p-type and “n” means n-type. Here, the low-side C-MOS circuit that transmits an input signal of the level shift circuit and the high-side C-MOS circuit that transmits an output signal of the level shift circuit to the upper arm IGBT 115 are shown as the peripheral circuits.
As shown in FIG. 10, when the input signal (H-IN) of the low-side circuit is input, this signal is input to a gate of an n-channel MOSFET 41 of the level-up circuit via the C-MOS circuit of the low-side circuit. The n-channel MOSFET 41 is turned on/off by this signal, and an output signal of the level-up circuit is output from an output part 101. The C-MOS circuit of the high-side circuit is turned on/off by this signal, and the output signal (H-OUT) is output. This output signal is converted into a Vs-based signal. This output signal is input to the gate of the upper arm IGBT 115, turning the upper arm IGBT 115 on/off. The level-up circuit shown in FIG. 10 is required when the upper arm IGBT 115 is of an n-channel type.
As shown in FIG. 11, the level-down circuit is formed of a p-channel MOSFET 43 and a level shift resistor 72. A diode 76 is connected in parallel to the level shift resistor. A signal of the ALM-IN is input to a gate of the C-MOS circuit of the high-side circuit, and an output signal of the C-MOS circuit is input to a gate of the p-channel MOSFET 43 of the level-down circuit. By turning on/off the p-channel MOSFET 43 with this signal, a low-side signal is output from an output part 102 of the level-down circuit, and a signal that is leveled down from the output side of the C-MOS circuit of the low-side circuit is output from the ALM-OUT to the low side, in the form of a detection signal.
The switching power device is widely used in many fields, including motor control inverters, large-volume PDPs (plasma display panels), power supplies for liquid crystal panels, and inverters for home electronics such as air conditioners and lights.
These motors and lights become inductance loads shown in FIG. 9. Therefore, the Vs terminal or the H-VDD terminal of the HVIC are affected by parasitic inductance components from wires on a printed board or cables extending to the loads. Due to the parasitic inductance components, the Vs terminal or the H-VDD terminal of the HVIC 111 are displaced to a negative-potential side in relation to the ground (the GND terminal shown in FIG. 9) upon switching where the upper arm IGBT 115 is turned off or the lower arm IGBT 114 is turned on. This displacement is a cause of an erroneous operation or a latchup of the high-side circuit, destroying the elements.
FIG. 12 is a detail diagram of a level shift circuit diagram of the conventional HVIC. FIG. 12(a) is a level-up circuit diagram, and FIG. 12(b) is a level-down circuit diagram. The level-up circuit shown in FIG. 12(a) has a level shift resistor 71, and the n-channel MOSFET 41 to which the level shift resistor 71 and a drain are connected, wherein the connection between the level shift resistor 71 and the n-channel MOSFET 41 is configured as the output part 101 of the level-up circuit.
As described above, the diode 75 is connected in parallel to the level shift resistor 71 in order to prevent the level shift resistor 71 from being destroyed when the potential of the H-VDD becomes significantly lower than the GND potential (when an excessive negative-voltage surge is applied). When an overvoltage is applied to the H-VDD, the diode 75 functions to prevent the application of an excessive voltage to the gate of the MOSFET of the C-MOS circuit of the high-side circuit. Normally, a zener diode is frequently used as the diode 75. Furthermore, a body diode 42 is embedded inverse-parallel in the n-channel MOSFET 41.
The level-down circuit shown in FIG. 12(b), on the other hand, has a drain of the p-channel MOSFET 43 and the level shift resistor 72 connected to this drain, wherein the connection between the level shift resistor 72 and the p-channel MOSFET 43 is configured as the output part 102 of the level-down circuit.
The diode 76 is connected in parallel to the level shift resistor 72 in order to prevent the level shift resistor 72 from being destroyed when the potential of the H-VDD becomes significantly lower than the GND potential. Furthermore, when an overvoltage is applied to the H-VDD during an ON operation of the p-channel MOSFET 43, the diode 76 functions to prevent the application of an overvoltage to the gate of the MOSFET of the C-MOS circuit of the low-side circuit. Moreover, a body diode 44 is connected in inverse-parallel to the p-channel MOSFET 43.
FIG. 13 is a cross-sectional diagram showing substantial parts of a logic part, a level-up circuit part, and a high-voltage junction terminating region (HVJT) of each of high-side and low-side circuits of a conventional self-separation type high-voltage integrated circuit device 500. Note that referential marks a to j shown in FIG. 13 represent electrodes formed on each of the regions. Reference numeral 21 represents a p-offset region. Reference numerals 22 to 24, 26 to 28, 32 to 34, and 36 to 38 represent source, drain and contact regions. Reference numerals 25, 29, 35 and 39 represent gate electrodes.
As shown in FIG. 13, an n-well region 2 and n-well region 3 are formed on a surface layer of a p-semiconductor substrate 1 connected to a GND potential. A C-MOS circuit of a low-side circuit and the like, for example, are formed within the n-well region 2. A level shift circuit or a C-MOS circuit of a high-side circuit and the like, for example, are formed in the n-well region 3.
The level shift n-channel MOSFET 41 has an n-well region 4, a p-region 51 in contact with the n-well region 4, an n-source region 53 and a p-contact region 54 that are formed on a surface layer of the p-region 51, an n-drain region 52 formed on a surface layer of the n-well region 4, and a gate electrode 55 that is formed between the n-source region 53 and the n-drain region 52 and on the p-region 51 with a gate oxide film therebetween.
The drain region 52 of the n-channel MOSFET 41 is connected to the H-VDD via the level shift resistor 71 by a surface metal wire. The high-voltage integrated circuit device 500 has the connection between the drain region 52 of the n-channel MOSFET 41 and the level shift resistor 71 as the output part 101.
The output part 101 outputs a low potential when the level-up n-channel MOSFET 41 is turned on, and outputs a high potential when the level-up n-channel MOSFET 41 is turned off. For this reason, the high-voltage integrated circuit device 500 can perform a level shift operation for transmitting signals between different reference potentials.
As described above, a surge of negative potential in relation to the GND potential is input the Vs terminal at the time when the upper arm IGBT 115 is turned off. This voltage Vs can be calculated using the following equation (1).Vs=L×dl/dt  (1)
When the voltage Vs is lower than GND potential—(Vsupply+Vf), an internal parasitic diode of a semiconductor chip starts flowing. Note that Vsupply is a battery voltage of the high-side power supply 113 or a battery voltage between ends of a bootstrap capacitor, not shown. Referential mark Vf indicates a forward voltage drop of parasitic diodes 45, 46.
When the voltage Vf is significantly pulled toward the negative side, an overcurrent flows in the chip, causing an erroneous operation in the high-side circuit or damaging the chip. During the period in which the voltage Vs is pulled toward the negative side, it takes about several hundreds of ns to 500 ns for a spike-like negative surge of approximately −30 V to be input to the Vs terminal, in proportion to a product of dl1/dt that is obtained from a period for turning off an on-current 11 flowing in the parasitic inductance component (L1) and the IGBT 115, the parasitic inductance component being generated in a wire on the printed board or a cable to the load.
FIG. 14 is a layout diagram showing substantial parts such as the high-side circuit shown in FIG. 13, a level shifter, and the like. An H-VDD pad, an H-OUT pad, a Vs pad, and an intermediate-potential region are formed in the n-well region 3, a high-potential region. The intermediate-potential region includes a p-offset region 31 and a p-drain region 34. A belt-like n-contact region 62 is formed on a surface layer on an outer circumference of the n-well region 3. First pickup electrodes 81 are scattered on the n-contact region 62. The n-well region 4 is formed so as to surround the n-well region 3. A p-region 61 is formed so as to surround the n-well region 4.
A belt-like p-contact region 56 is formed on a surface layer of the p-region 61. Second pickup electrodes 82 are scattered on the p-contact region 56. The n-well region 2, which is a low-potential region, is formed so as to surround the p-region 61. The low-side circuit shown in FIG. 13 is formed in the n-well region 2. A level shifter is formed on a surface layer of the p-region 51 between the n-contact region 62 and the p-region 61. The n-contact region 62 and the p-region 61, as well as the n-well region and the p-region 51 that are sandwiched between these regions, configure a high-voltage junction terminating region. The p-region 51 and the n-well region 4 that form the level shifter are in contact with each other.
In order to reduce the size of the chip by efficiently arranging the regions described above, a part of the intermediate-potential region is disposed in proximity to the n-contact region 62. This section proximal to the n-contact region 62 is denoted with “E.” The section E proximal to the n-contact region 62 is where the intermediate-potential region faces the high-voltage junction terminating region and where a distance W between the intermediate-potential region and the high-voltage junction terminating region is the smallest (referred to as “opposition section E” hereinafter).
As this type of high-voltage integrated circuit, there has been disclosed a high-voltage integrated circuit chip, which has a resistor between a substrate and a ground to limit a current flowing through a negative-voltage spike in a circuit that protects a high-voltage integrated circuit driving a power transistor having a half-bridge configuration and expects an excessive negative movement in an output node (point) (see Patent Literature 1, for example).
Moreover, as a high-voltage integrated circuit device, there has been disclosed a device that diminishes the impact of a reverse bias by inserting a diode between a drain electrode of a switching element belonging to a level shifter and a gate electrode of a MOS transistor belonging to an amplifier (C-MOS circuit) (see Patent Literature 2, for example).
In addition, as another high-voltage integrated circuit device, there has been disclosed a device in which a drain of a switching element belonging to a level shifter, a level shift resistor, and a current restricting resistor are connected to one another in series, and an interval between the level shift resistor and the current restricting resistor is configured as an output part of a level-up circuit (see Patent Literature 3, for example).
As yet another high-voltage integrated circuit device, the following device is disclosed. In this device, a high-voltage diode (D3) is provided between a common ground node (COM) and a virtual ground node (VS) within a high-voltage control circuit (HVIC) by using a common substrate region. This configuration can reliably prevent a decrease in high-potential side power supply voltage, which is caused by an undershoot of a negative voltage occurring at a high-potential side reference potential (virtual ground VS), in a power device driving circuit (see Patent Literature 4, for example).
Patent Literature 1: Japanese Patent Publication No. 3346763
Patent Literature 2: Japanese Patent Application Publication No. 2001-25235
Patent Literature 3: Japanese Patent Application Publication No. 2008-301160
Patent Literature 4: Japanese Patent Application Publication No. 2010-263116
However, the conventional high-voltage integrated circuit devices described above have the following problems. A case example is described in which, at the connection between the switching power device and the HVIC in FIG. 9, the Vss has a potential of approximately 1200 V and the H-VDD has a potential higher than that of the Vs by approximately 15 V. When the upper arm IGBT 115 is operated and the lower arm IGBT 114 is off, a current flows from the upper arm IGBT 115 to the L load 118.
In this state, when the upper arm IGBT 115 is turned off, the L load 118 attempts to maintain the current. As a result, a current flows from the GND via the lower arm FWD 116, making the potential of the Vs terminal lower than the GND potential to approximately −30 V. When the potential of the Vs terminal becomes approximately −30 V, the potential of the H-VDD terminal becomes approximately −15 V.
In the structure of the high-voltage integrated circuit device shown in FIG. 13, the potentials of the p-semiconductor substrate 1 and the p-region 61 are equivalent to the GND potential. A case example is described in which the potential of the Vs terminal decreases to a level where the potentials of the n-well regions 3 and 4 become lower than the GND potential.
The parasitic diode 45 configured by the p-semiconductor substrate 1 and the n-well region 3, and the parasitic diode 46 configured by the p-region 61 and the n-well region 4 are forward-biased, and consequently a large current flows. This current flows via a space between the gate and the source of the IGBT 115. Because this path does not contain any resistor components for restricting the current, the current flowing therethrough becomes an extremely large pulse current. This pulse current destroys the HVIC or causes an erroneous operation therein.
In addition, applying a negative-voltage surge to the Vs pad (terminal) or the H-VDD pad (terminal) in FIGS. 13 and 14 causes electron hole injection where electron holes are injected from the p-region 61 to the n-well region 4 configuring the parasitic diode 46. Especially in the opposition section E of the high-voltage junction terminating region, whose distance W to the intermediate-potential region is short, the resistance of the n-well region 4 (a cathode resistance of the parasitic diode 46) between the intermediate-potential region and the p-region 61 becomes small compared to the other sections. Therefore, the amount of electron holes between the p-region 61 and the n-well region 4 is large compared to the other sections.
The electron holes injected into the n-well region 4 flow to the p-offset region 31 and the p-drain region 36 (when an ON signal is input to the gate electrode 39), which are Vs potential regions with negative potentials, through below the n-contact region 62. The electron holes entering the p-offset region 31 are pulled out from the p-contact region 38 toward the Vs terminal.
However, some of the electron holes enter below the n-source region 37 and becomes a gate current of a parasitic npn transistor configured by the n-source region 37, the p-offset region 31, and the n-well region 3. When the parasitic npn transistor is turned on, the logic part of the high-side circuit is likely to be operated erroneously.
Also, the electron holes entering below the n-source region 37 turn on (latch up) a parasitic thyristor configured by the n-source region 37, the p-offset region 31, the n-well region 3, and the p-semiconductor substrate 1, destroying the high-side circuit. When some of the electron holes flow toward the p-drain region 34 through the n-well region 3, the logic part of the high-side circuit is still likely to be operated erroneously.
In the technology of Patent Literature 1 described above, the resistor for limiting a current is connected to the interval between the GND (earth ground) terminal and the substrate. This technology does not mention about connections of the sections other than this interval. This resistor is formed of a polysilicon layer. Therefore, when a large pulse current (several A to several tens of A) of negative voltage transiently flows to the parasitic diode between the Vs terminal and the GND terminal, the polysilicon layer might be thermally dissolved and destroyed.
In the technology of Patent Literature 2 described above, the diode is connected in order to diminish the impact of a reverse bias. This technology, however, does not mention about a resistor or a layout method that limits a current of a body diode or a parasitic diode when the potential of the H-VDD becomes negative due to the L load.
In the technology of Patent Literature 3 described above, the current restricting resistor is connected to a path between the high-potential side (H-VDD) and the low-potential side (ground) of the Vs-based low-voltage power supply of the level shift circuit. In this manner, a body diode or a parasitic diode of the n-channel MOSFET is prevented from being destroyed by an overcurrent, and a section of the level shift circuit that has a small current capacity is also prevented from being destroyed by an overcurrent. This technology, however, does not mention about how to prevent a parasitic erroneous operation (erroneous inversion) of the Vs-based high-side circuit.
In the technology of Patent Literature 4 described above, the high-voltage diode (D3) is provided between the Vs terminal and the substrate of the high-voltage control circuit (HVIC) on the GND potential side, but does not mention about providing the high-voltage diode (D3) between a VB terminal, which is a bootstrap power supply node, and the substrate of the high-voltage control circuit (HVIC) on the GND potential side.